More and more communication systems support multiple standards and protocols. These systems rely on compressed operating modes that divide timing frames into sub periods and assign these periods to different protocols. The sub periods allow probing and setting up of new communication links. These require an advanced radio transceiver and, more often than not, duplicate frequency synthesizers to support fast switching.
Frequency synthesizers based on phase-locked loops (PLL) use a feedback loop to create an agile, low-noise signal. The feedback loop helps to minimize noise in track mode but tends to increase the switching time in acquisition mode, making it difficult to optimize the phase-locked loop's overall performance. As such, it would therefore be advantageous to adjust the parameters associated with the phase-locked loop and optimize them according to its mode of operation.